#include "app.h"

void savestate_mem(struct MD_SAVESTATE *s)
{
	memset(s,0,sizeof(struct MD_SAVESTATE));
	s->drmd_lines_per_frame=drmd.lines_per_frame;
	s->drmd_vdp_line=drmd.vdp_line; 
	s->drmd_vdp_status=drmd.vdp_status;
	s->drmd_vdp_addr=drmd.vdp_addr;
	s->drmd_vdp_addr_latch=drmd.vdp_addr_latch;
	s->drmd_gamma=drmd.gamma;
	s->drmd_cpl_m68k=drmd.cpl_m68k;
	s->drmd_cpl_z80=drmd.cpl_z80;
	s->drmd_padselect=drmd.padselect;
	s->drmd_zbusreq=drmd.zbusreq;
	s->drmd_zbusack=drmd.zbusack;
	s->drmd_zreset=drmd.zreset;
	s->drmd_vdp_reg0=drmd.vdp_reg0;
	s->drmd_vdp_reg1=drmd.vdp_reg1;
	s->drmd_vdp_reg2=drmd.vdp_reg2;
	s->drmd_vdp_reg3=drmd.vdp_reg3;
	s->drmd_vdp_reg4=drmd.vdp_reg4;
	s->drmd_vdp_reg5=drmd.vdp_reg5;
	s->drmd_vdp_reg6=drmd.vdp_reg6;
	s->drmd_vdp_reg7=drmd.vdp_reg7;
	s->drmd_vdp_reg8=drmd.vdp_reg8;
	s->drmd_vdp_reg9=drmd.vdp_reg9;
	s->drmd_vdp_reg10=drmd.vdp_reg10;
	s->drmd_vdp_reg11=drmd.vdp_reg11;
	s->drmd_vdp_reg12=drmd.vdp_reg12;
	s->drmd_vdp_reg13=drmd.vdp_reg13;
	s->drmd_vdp_reg14=drmd.vdp_reg14;
	s->drmd_vdp_reg15=drmd.vdp_reg15;
	s->drmd_vdp_reg16=drmd.vdp_reg16;
	s->drmd_vdp_reg17=drmd.vdp_reg17;
	s->drmd_vdp_reg18=drmd.vdp_reg18;
	s->drmd_vdp_reg19=drmd.vdp_reg19;
	s->drmd_vdp_reg20=drmd.vdp_reg20;
	s->drmd_vdp_reg21=drmd.vdp_reg21;
	s->drmd_vdp_reg22=drmd.vdp_reg22;
	s->drmd_vdp_reg23=drmd.vdp_reg23;
	s->drmd_vdp_reg24=drmd.vdp_reg24;
	s->drmd_vdp_reg25=drmd.vdp_reg25;
	s->drmd_vdp_reg26=drmd.vdp_reg26;
	s->drmd_vdp_reg27=drmd.vdp_reg27;
	s->drmd_vdp_reg28=drmd.vdp_reg28;
	s->drmd_vdp_reg29=drmd.vdp_reg29;
	s->drmd_vdp_reg30=drmd.vdp_reg30;
	s->drmd_vdp_reg31=drmd.vdp_reg31;
	s->drmd_vdp_reg32=drmd.vdp_reg32;
	s->drmd_vdp_counter=drmd.vdp_counter;
	s->drmd_hint_pending=drmd.hint_pending;
	s->drmd_vint_pending=drmd.vint_pending;
	s->drmd_vdp_pending=drmd.vdp_pending;
	s->drmd_vdp_code=drmd.vdp_code;
	s->drmd_vdp_dma_fill=drmd.vdp_dma_fill;
	s->drmd_pad_1_status=drmd.pad_1_status;
	s->drmd_pad_1_com=drmd.pad_1_com;
	s->drmd_pad_2_status=drmd.pad_2_status;
	s->drmd_pad_2_com=drmd.pad_2_com;
	s->drmd_sram_start=drmd.sram_start;
	s->drmd_sram_end=drmd.sram_end;
	s->drmd_sram=drmd.sram;
	s->drmd_region=drmd.region;
	s->drmd_sram_flags=drmd.sram_flags;
	s->drmd_cpl_fm=drmd.cpl_fm;
	memcpy(s->drmd_genesis_rom_banks,drmd.genesis_rom_banks,0x10);
	s->drmd_pad=drmd.pad;
	s->drmd_pad_1_counter=drmd.pad_1_counter;
	s->drmd_pad_1_delay=drmd.pad_1_delay;
	s->drmd_pad_2_counter=drmd.pad_2_counter;
	s->drmd_pad_2_delay=drmd.pad_2_delay;
	s->drz80_Z80PC=drz80.Z80PC;
	s->drz80_Z80A=drz80.Z80A;
	s->drz80_Z80F=drz80.Z80F;
	s->drz80_Z80BC=drz80.Z80BC;
	s->drz80_Z80DE=drz80.Z80DE;
	s->drz80_Z80HL=drz80.Z80HL;
	s->drz80_Z80SP=drz80.Z80SP;
	s->drz80_Z80PC_BASE=drz80.Z80PC_BASE;
	s->drz80_Z80SP_BASE=drz80.Z80SP_BASE;
	s->drz80_Z80IX=drz80.Z80IX;
	s->drz80_Z80IY=drz80.Z80IY;
	s->drz80_Z80I=drz80.Z80I;
	s->drz80_Z80A2=drz80.Z80A2;
	s->drz80_Z80F2=drz80.Z80F2;
	s->drz80_Z80BC2=drz80.Z80BC2;
	s->drz80_Z80DE2=drz80.Z80DE2;
	s->drz80_Z80HL2=drz80.Z80HL2;   
	s->drz80_Z80_IRQ=drz80.Z80_IRQ;
	s->drz80_Z80IF=drz80.Z80IF;
	s->drz80_Z80IM=drz80.Z80IM;
	s->drz80_Z80R=drz80.Z80R;
	s->drz80_z80irqvector=drz80.z80irqvector;
	s->drz80_Z80_NMI=drz80.Z80_NMI;
#ifdef EMU_C68K
	CyclonePack(&cyclone, s->cyclone);
#endif
	memcpy(s->work_ram,work_ram,0x10000);
	memcpy(&s->vram,&vram,0x10000);
	memcpy(s->zram,zram,0x4000);
	memcpy(s->cram,cram,0x80);
	memcpy(s->vsram,vsram,0x80);
	memcpy(&s->SL3,&SL3,sizeof(SL3));
	memcpy(&s->ST,&ST,sizeof(ST));
	memcpy(&s->OPN,&OPN,sizeof(OPN));
	memcpy(&s->CH,&CH,sizeof(CH));
	s->dacout=dacout;	
	s->dacen=dacen;
	memcpy(s->OPN_pan,OPN_pan,6*2); 
	memcpy(&s->PSG,&PSG,sizeof(PSG));
	s->YMOPN_ST_dt_tab=(unsigned int)&YMOPN_ST_dt_tab[0];
	memcpy(s->sram,sram,0x10000);
}

void loadstate_mem(const struct MD_SAVESTATE *s)
{
	int x=0,y=0;
	unsigned int old_DT_Table;

	drmd.lines_per_frame=s->drmd_lines_per_frame;
	drmd.vdp_line=s->drmd_vdp_line; 
	drmd.vdp_status=s->drmd_vdp_status;
	drmd.vdp_addr=s->drmd_vdp_addr;
	drmd.vdp_addr_latch=s->drmd_vdp_addr_latch;
	drmd.gamma=s->drmd_gamma;
	drmd.cpl_m68k=s->drmd_cpl_m68k;
	drmd.cpl_z80=s->drmd_cpl_z80;
	drmd.padselect=s->drmd_padselect;
	drmd.zbusreq=s->drmd_zbusreq;
	drmd.zbusack=s->drmd_zbusack;
	drmd.zreset=s->drmd_zreset;
	drmd.vdp_reg0=s->drmd_vdp_reg0;
	drmd.vdp_reg1=s->drmd_vdp_reg1;
	drmd.vdp_reg2=s->drmd_vdp_reg2;
	drmd.vdp_reg3=s->drmd_vdp_reg3;
	drmd.vdp_reg4=s->drmd_vdp_reg4;
	drmd.vdp_reg5=s->drmd_vdp_reg5;
	drmd.vdp_reg6=s->drmd_vdp_reg6;
	drmd.vdp_reg7=s->drmd_vdp_reg7;
	drmd.vdp_reg8=s->drmd_vdp_reg8;
	drmd.vdp_reg9=s->drmd_vdp_reg9;
	drmd.vdp_reg10=s->drmd_vdp_reg10;
	drmd.vdp_reg11=s->drmd_vdp_reg11;
	drmd.vdp_reg12=s->drmd_vdp_reg12;
	drmd.vdp_reg13=s->drmd_vdp_reg13;
	drmd.vdp_reg14=s->drmd_vdp_reg14;
	drmd.vdp_reg15=s->drmd_vdp_reg15;
	drmd.vdp_reg16=s->drmd_vdp_reg16;
	drmd.vdp_reg17=s->drmd_vdp_reg17;
	drmd.vdp_reg18=s->drmd_vdp_reg18;
	drmd.vdp_reg19=s->drmd_vdp_reg19;
	drmd.vdp_reg20=s->drmd_vdp_reg20;
	drmd.vdp_reg21=s->drmd_vdp_reg21;
	drmd.vdp_reg22=s->drmd_vdp_reg22;
	drmd.vdp_reg23=s->drmd_vdp_reg23;
	drmd.vdp_reg24=s->drmd_vdp_reg24;
	drmd.vdp_reg25=s->drmd_vdp_reg25;
	drmd.vdp_reg26=s->drmd_vdp_reg26;
	drmd.vdp_reg27=s->drmd_vdp_reg27;
	drmd.vdp_reg28=s->drmd_vdp_reg28;
	drmd.vdp_reg29=s->drmd_vdp_reg29;
	drmd.vdp_reg30=s->drmd_vdp_reg30;
	drmd.vdp_reg31=s->drmd_vdp_reg31;
	drmd.vdp_reg32=s->drmd_vdp_reg32;
	drmd.vdp_counter=s->drmd_vdp_counter;
	drmd.hint_pending=s->drmd_hint_pending;
	drmd.vint_pending=s->drmd_vint_pending;
	drmd.vdp_pending=s->drmd_vdp_pending;
	drmd.vdp_code=s->drmd_vdp_code;
	drmd.vdp_dma_fill=s->drmd_vdp_dma_fill;
	drmd.pad_1_status=s->drmd_pad_1_status;
	drmd.pad_1_com=s->drmd_pad_1_com;
	drmd.pad_2_status=s->drmd_pad_2_status;
	drmd.pad_2_com=s->drmd_pad_2_com;
	drmd.sram_start=s->drmd_sram_start;
	drmd.sram_end=s->drmd_sram_end;
	drmd.sram=s->drmd_sram;
	drmd.region=s->drmd_region;
	drmd.sram_flags=s->drmd_sram_flags;
	drmd.cpl_fm=s->drmd_cpl_fm;
	memcpy(drmd.genesis_rom_banks,s->drmd_genesis_rom_banks,0x10);
	drmd.pad=s->drmd_pad;
	drmd.pad_1_counter=s->drmd_pad_1_counter;
	drmd.pad_1_delay=s->drmd_pad_1_delay;
	drmd.pad_2_counter=s->drmd_pad_2_counter;
	drmd.pad_2_delay=s->drmd_pad_2_delay;
	drz80.Z80PC=s->drz80_Z80PC;
	drz80.Z80A=s->drz80_Z80A;
	drz80.Z80F=s->drz80_Z80F;
	drz80.Z80BC=s->drz80_Z80BC;
	drz80.Z80DE=s->drz80_Z80DE;
	drz80.Z80HL=s->drz80_Z80HL;
	drz80.Z80SP=s->drz80_Z80SP;
	drz80.Z80PC_BASE=s->drz80_Z80PC_BASE;
	drz80.Z80SP_BASE=s->drz80_Z80SP_BASE;
	drz80.Z80IX=s->drz80_Z80IX;
	drz80.Z80IY=s->drz80_Z80IY;
	drz80.Z80I=s->drz80_Z80I;
	drz80.Z80A2=s->drz80_Z80A2;
	drz80.Z80F2=s->drz80_Z80F2;
	drz80.Z80BC2=s->drz80_Z80BC2;
	drz80.Z80DE2=s->drz80_Z80DE2;
	drz80.Z80HL2=s->drz80_Z80HL2;   
	drz80.Z80_IRQ=s->drz80_Z80_IRQ;
	drz80.Z80IF=s->drz80_Z80IF;
	drz80.Z80IM=s->drz80_Z80IM;
	drz80.Z80R=s->drz80_Z80R;
	drz80.z80irqvector=s->drz80_z80irqvector;
	drz80.Z80_NMI=s->drz80_Z80_NMI;
#ifdef EMU_C68K
	CycloneUnpack(&cyclone, s->cyclone);
#endif
	memcpy(work_ram,s->work_ram,0x10000);
	memcpy(&vram,&s->vram,0x10000);
	memcpy(zram,s->zram,0x4000);
	memcpy(cram,s->cram,0x80);
	memcpy(vsram,s->vsram,0x80);
	memcpy(&SL3,&s->SL3,sizeof(SL3));
	memcpy(&ST,&s->ST,sizeof(ST));
	memcpy(&OPN,&s->OPN,sizeof(OPN));
	memcpy(&CH,&s->CH,sizeof(CH));
	dacout=s->dacout;	
	dacen=s->dacen;
	memcpy(OPN_pan,s->OPN_pan,6*2); 
	memcpy(&PSG,&s->PSG,sizeof(PSG));
	old_DT_Table=s->YMOPN_ST_dt_tab;
	memcpy(sram,s->sram,0x10000);
	
				
	for(x=0;x<6;x++)
	{
	for(y=0;y<4;y++)
	{
	CH[x].SLOT[y].DT=(int*)(((unsigned int)&YMOPN_ST_dt_tab[0])+((unsigned int)(CH[x].SLOT[y].DT)-old_DT_Table));
	}
	}
}


